1. Field of the Invention
The present invention relates to an amplifying circuit, particularly, to an amplifying circuit with a pull-up circuit and a pull-down circuit for increasing the slew rate of the amplifying circuit.
2. Description of the Prior Art
An LCD display is often desirable for having high resolution, small volume, a high stand by period, and low power consumption. I future designs, the driving IC of the LCD would also need chip area reduction and low power consumption. Thus an amplifier capable of enabling a system having a load is necessary for the structure of the driver IC. For such operation, however, the amplifying circuit may have the problem of static power consumption, large chip area, and low slew rate.
Please refer to FIG. 1, FIG. 1 illustrates a prior art amplifying circuit 100 that can increase the slew rate. As shown in FIG. 1, the amplifying circuit 100 comprises an operational amplifier 110, and a slew rate enhancing circuit 120. It should be noted that since the circuit structure of the operational amplifier 110 is well known by persons skilled in the art, it is omitted for brevity. The slew rate enhancing circuit 120 comprises a pull-up transistor 122 and a pull-down transistor 124, wherein the pull-up transistor 122 consist of N type MOS transistors having a first terminal (source) coupled to a output terminal of the amplifier 110, a second terminal (drain) coupled to a voltage source (Vdd), and a controlling terminal (gate) coupled to an input terminal of the amplifier 110. Additionally, the pull-down transistor 124 consists of P type MOS transistors having a first terminal (source) coupled to a output terminal of the amplifier 110 and the first terminal of the pull-up transistor 122, a second terminal (drain) coupled to ground level, and a controlling terminal (gate) coupled to an input terminal of the amplifier 110 and the controlling terminal (gate) of the pull-up transistor 122. In this way, a source follower consisting of PMOS/NMOS transistors is formed.
Operation of the prior art amplifying circuit 100 is described as follows. If the input voltage Vi is larger than the output voltage Vo above a threshold voltage Vth, the pull-up transistor 122 turns on and the pull-down transistor 124 turns off, such that the output voltage will rapidly pull up. Conversely, if the input voltage Vi is smaller than the output voltage Vo above a threshold voltage Vth, the pull-up transistor 122 turns off and the pull-down transistor 124 turns on, such that the output voltage will be rapidly pull down. The disadvantage of the prior art amplifying circuit 100 is that the voltage difference between the input terminal and the output terminal requires being greater than the threshold voltage Vth in order to turn on or off the slew rate enhancing circuit 120, so that the operation voltage region for enhancing slew rate decreases. Also, if the body effect of the source follower exists, the efficiency will become worse.
Some inventions are disclosed for solving the problem of increasing slew rate. For example, U.S. Pat. No. 6,392,485 discloses a related invention, which utilizes a feedback loop signal to control static operation of the differential input stage to solve the problem slow slew rate. Also, U.S. Pat. No. 6,700,422 discloses a source follower consisting of PMOS/NMOS transistors to solve the problem of too small a slew rate due to output stage current and load capacitance.
As described above, to achieve low static power consumption, small chip area, and high slew rate while utilizing an amplifying circuit to meet high load demands is an important problem for circuit designers.